1. Field of the Invention
The present invention relates to a transversal filter circuit, more particularly, to a transversal filter circuit having a simplified circuit construction and in which serial binary data are processed.
2. Description of the Prior Art
Transversal filters are employed in various applications, for example, as an echo canceller in a communication system, and as a ghost canceller for an audio signal or a video signal.
Various types of circuit constructions have been proposed for such transversal filter circuits, for example, a transposed transversal shown in FIG. 17 is known. In particular, a time series signal having components which are continued for a long time, such as a video signal is processed by the transposed transversal filter to reduce noise therein.
The transposed transversal filter circuit shown in FIG. 17 includes a plurality of tap circuits (unit elements in the transversal filter circuit) connected in series, each constructed by a multiplier 1 for calculating a product of an input data X and a coefficient Kx, where x=1, 2, . . . , n, an adder 2 for adding the multiplied result and a result obtained at a tap located at a preceding position in a data stream (hereinafter, called a preceding stage), and a unit time delaying circuit 3 for delaying the added result by a unit of time. A filtering processed result Y is finally output from a unit time delaying circuit provided at a final stage tap circuit.
Assuming that such a transversal filter circuit is applied, for example, as a ghost canceller for a video signal, a long time ghost cancellation of the video signal is required, and as a result, a transversal filter including several hundreds of tap circuits must be constructed.
Assuming that such a transversal filter circuit is constructed, it would be mounted in a building block manner in which a plurality of modules of semiconductor (LSI) chips are combined as shown in FIG. 18. In FIG. 18, LSI chips CHIP1 to CHIP5, each of which includes a transversal filter having 128 taps, are serially connected. The first chip CHIP1 includes two sets of FIR transversal filters, each of which has 64 taps and which are used by changing a connection thereat in parallel or in series, and IIR transversal filters, each of which has 128 taps, are constructed to thus connect a total of 512 taps in series.
A video signal 1 is supplied to the first chip CHIP1, an output of the chip CHIP1, as a cascade sum output 1, is supplied to an adder ADR, an output from the final stage chip CHIP5, as a cascade sum output 2, is supplied to the adder, and the added value as a second video signal, is supplied to the chips CHIP1 to CHIP5. On the other hand, a tap coefficient data supplied from outside, and the above video signal, are supplied to the respective chips, and a filtering is processed in accordance with an algorithm on the basis of a construction of the transversal filter circuit shown in FIG. 17.
A fundamental construction of each tap circuit in such multiple stage type transversal filter comprises the multiplier 1, the adder 2 and the unit time delaying circuit 3, specifically a register, described above. When a construction of multiple of taps is adopted, a plurality of tap circuits, each being this type of tap circuit, are connected in series. Now, the fundamental construction of the unit tap circuit will be described.
A multiplication of the tap coefficient and the input data, as shown in FIG. 19, normally, can be serially processed by a plurality of operations, in each of which a partial product is calculated, the resultant partial product is added to a previous sum of partial products obtained until a preceding operation time in consideration of an adjustment of decimal (binary) point positions among the partial products, to adjust the decimal point positions thereof. Under such an algorithm, when the tap coefficient and the input data are both serial binary date, a multiplication of one bit thereof can be carried out using a single AND gate, and thus, the circuit construction of a serial multiplier can be simplified. (If a normal multiplication of the tap coefficient and the input data is carried out, a multiplication circuit having a complex structure is required.) Accordingly, as the multiplier 1, a serial multiplier which consecutively calculates and adds partial products a plurality of times, is provided in each tap.
A parallel multiplication method is also known, but a circuit construction thereof is complex, and further since it is not directly related to the present invention, a description thereof is omitted.
FIGS. 20 and 21 show circuit constructions of prior art serial multiplication circuits.
A serial multiplier shown in FIG. 20 is constructed by connecting a coefficient register 122 holding tap coefficient, an input data register 142 holding an input data and serially outputting same, a partial product calculation circuit 160, a parallel adder 180, an output register 112, and an decimal point position adjustment circuit 900, as shown in the drawing. An operation of this serial multiplier will be briefly described. The partial product calculation circuit 160 calculates a partial product of the tap coefficient output from the coefficient register 122 and one bit data of the input data output from the input data register 142, and the adder 180 adds a current calculated partial product to a sum of a partial products obtained at a preceding timing and held in a holder register 182. The holding register 182 is cleared at a first time of every operation cycle, and is used for temporary storing the result from the adder 180. The decimal point position adjustment circuit 900 is a unidirectional one bit shift register which adjusts a decimal point position of the added result at the preceding timing, to add same to a partial product obtained at a next timing, as shown in FIG. 19.
In the example shown in FIG. 19, partial product calculations are carried out four times in every operation cycle. Hereinafter, this cycle for obtaining the partial products is called a partial product calculation cycle. In this example, therefore, one operation cycle consists of four partial product calculation cycles.
The serial multiplier shown in FIG. 21 is also constructed by connecting a coefficient register 122, an input data register 142, a partial product calculation circuit 160, a decimal point position adjustment circuit 902, a parallel adder 110, and a holding register 182, as shown in the drawing. The shift multiplier carries out a multiplication calculation in accordance with the algorithm shown in FIG. 19, and a result thereof is similar to that obtained by the serial multiplier shown in FIG. 20.
A difference in the circuit construction of the serial multiplier shown in FIG. 20 and the serial multiplier shown in FIG. 21 is a position at which the decimal point position adjustment circuits 900 and 902 are located. In the former, the decimal point position adjustment circuit 900 is located at a position following by the adder 180 or at a position preceding the adder 180, but in the latter case, the decimal point position adjustment circuit 902 is provided between the partial product calculation circuit 160 and the adder 180.
Such serial multipliers suffer from the following disadvantages.
In the serial multiplier shown in FIG. 20, since a decimal point position varies during the calculation, if a result obtained by the serial multiplier is output to a next stage tap circuit, an adjustment of decimal point positions of data in adjacent tap circuits is required, to thereby adjust a difference between decimal points of the data in these tap circuits. In particular, if the output register is employed as an accumulator, the above difference becomes a serious disadvantage. As a result, the multiplier has a disadvantage of a complex circuit construction of a whole transversal filter due to the provision of decimal point position adjustment circuits for adjusting decimal point positions among the data in the tap circuits.
On the other hand, in the serial multiplier shown in FIG. 21, the problem of the above adjustment of the decimal point positions among the data in the tap circuits does not arise, since the adjustment of the decimal point positions is carried out therein, but complex circuits, such as barrel shifters must be employed as the decimal point position adjustment circuit 90, and as a result, the total circuit construction of the serial multiplier becomes complex. Consequently, the total construction of the transversal filter becomes complex, and thus such serial multiplier can not be practically employed.
In sum, when both of the serial multipliers are built into the LSI chip as shown in FIG. 18, a problem arises in that a size of one chip becomes large or the number of taps accommodated in one chip is reduced. The problem in question becomes particularly serious when a transversal filter circuit having several hundreds of taps is required.
The serial multipliers are not limited to application to the transversal filters, and thus, in case where many serial multipliers are used, the problems similar to the above problems may occur.
Next, a prior art circuit construction of one tap circuit shown in FIG. 17 and consisting of a multiplier 1, an adder (accumulator) 2, and a unit time delaying circuit 3, is shown in FIG. 22. Each tap circuit includes the serial multiplier shown in FIG. 20, and further, includes an adder 200, corresponding to the adder 2 shown in FIG. 17, and adding a result Y.sub.i-1 obtained at a preceding stage and a serial operation result C obtained at a tap circuit itself, and an output register 300, corresponding to the unit time delaying circuit 3 shown in FIG. 17, for holding the added result for a unit time and then outputting same to a next tap circuit.
The serial multiplier shown in FIG. 20 can be replaced by the serial multiplier shown in FIG. 21.
Considering the circuit construction of one tap circuit shown in FIG. 22, this circuit construction appears to be redundant due to a simple combination of the serial multiplier, the adder and the unit time delaying circuit, in addition to the above problem concerning the serial multiplier. Accordingly, a problem arises of a complex circuit construction of one tap circuit and of the total transversal filter circuit.
In the above circuit constructions, although a control circuit for driving and controlling these circuits is not shown, a clock used for driving these circuits can be an internal clock CLKi generated on the basis of an external clock CLKe having, for example, a frequency of 15 MHz; a frequency of the internal clock being 60 MHz, i.e., four times of the frequency of the external clock. The internal clock is generated internally, because it is difficult to supply a high frequency clock of 60 MHz from the outside of the chip. When a large number of taps is included in the transversal filter, and a signal processing time is shortened, a drive clock having a higher frequency is required.
As the circuit generating such an internal clock CLKi having a very high frequency, as shown in FIG. 23, a phase locked loop (PLL) circuit consisting of a phase comparator circuit 50, a loop filter 52, and a digital voltage controlled oscillation (VCO) circuit 58, can be employed. The VCO 58 includes a driver circuit 58A consisting of four series-connected current controlled drivers (inverters) controlled by an output of the loop filter 52, and a feed back inverter, and a clock generation circuit 58B generating an internal clock having a frequency which is based on the frequency of an external clock output from the driver circuit, the frequency of the internal clock being four times the frequency of the external clock.
The PLL shown in FIG. 23, however, includes the phase comparison circuit 50 and the loop filter 52 which are formed as analog circuits, and such analog circuits suffer from a problem such as jitter in a high frequency domain. Accordingly, if LSI chips of the transversal filter circuits are tested as devices, an instability in the operation of the analog circuit components may have an adverse effect on the digital circuit portions. A suitable testing means that does not impose such adverse conditions during the test is not known, and therefore a satisfactory test can not be carried out.
Further, the PLL shown in FIG. 23 suffers from the problem that an operation during test is very different from a normal operation, if a duty of the external clock CLKe is not maintained at 50%. This is because, the internal clock is merely generated by using AND gates or inverted AND gates, on the basis of the output signal from the one series-connected pair of current controlled drivers (inverters). The operation will be described in detail with reference to a timing chart shown in FIG. 24. When the output times of Q outputs from the drivers are shifted, a width of an AND logic thereof is directly varied. As a result, the generation timing of four clocks .phi..sub.1 to .phi..sub..DELTA. of the internal clock CLKi are shifted. Accordingly, the duty of the external clock must be accurately kept at 50%, but, it is difficult to maintain the duty of the external clock having a high frequency of 15 MHz or higher at 50%, and to apply same to the chips.
Considering the above, an object of the present invention is to provide a serial multiplier, per se, and a transversal filter circuit wherein a tap circuit construction is simplified and mounting efficiency is improved when multiple stage transversal filter circuits are installed in a chip, which generates an accurate internal clock, easily eliminates an adverse effect caused by analog circuit elements, and enables a test to be carried out under the same conditions as for a normal operation.